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1 of 39 november 28, 2011 ? 2011 integrated device technology, inc. ? idt and the idt logo are registered trademarks of integrated device technology, inc. device overview the 89HPES32T8G2 is a member of the idt precise? family of pci express? switching solutions. the pes32t8g2 is a 32-lane, 8-port switch optimized for pci express gen2 packet switching in high-perfor- mance applications. target applications include servers, storage, communications, embedded systems, and multi-host or intelligent i/o based systems with inter-domain communication. features ? high performance non-blocking switch architecture ? 32-lane 8-port pcie switch ? four x8 switch ports each of which can bifurcate to two x4 ports (total of eight x4 ports) ? integrated serdes supports 5.0 gt/s gen2 and 2.5 gt/s gen1 operation ? delivers up to 32 gbps (256 gbps) of switching capacity ? supports 128 bytes to 2 kb maximum payload size ? low latency cut-through architecture ? supports one virtual channel and eight traffic classes ? standards and compatibility ? pci express base specification 2.0 compliant ? implements the following optional pci express features ? advanced error reporting (aer) on all ports ? end-to-end crc (ecrc) ? access control services (acs) ? power budgeting enhanced capability ? device serial number enhanced capability ? sub-system id and sub-system vendor id capability ? internal error reporting ecn ? multicast ecn ? vga and isa enable ? l0s and l1 aspm ?ari ecn ? port configurability ? x4 and x8 ports ? ability to merge adjacent x4 ports to create a x8 port ? automatic per port link width negotiation (x8 x4 x2 x1) ? crosslink support ? automatic lane reversal ? autonomous and software managed link width and speed control ? per lane serdes configuration ? de-emphasis ? receive equalization ? drive strength ? initialization / configuration ? supports root (bios, os, or driver), serial eeprom, or smbus switch initialization ? common switch configurations are supported with pin strap- ping (no external components) ? supports in-system serial eeprom initialization/program- ming ? quality of service (qos) ? port arbitration ? round robin ? request metering ? idt proprietary feature that balances bandwidth among switch ports for maximum system throughput ? high performance switch core architecture ? combined input output queued (cioq) switch architecture with large buffers ? multicast ? compliant to the pci-sig multicast ecn ? supports arbitrary multicasting of posted transactions ? supports 64 multicast groups ? multicast overlay mechanism support ? ecrc regeneration support ? clocking ? supports 100 mhz and 125 mhz reference clock frequencies ? flexible clocking modes ? common clock ? non-common clock ? hot-plug and hot swap ? hot-plug controller on all ports ? hot-plug supported on all downstream switch ports ? all ports support hot-plug using low-cost external i 2 c i/o expanders ? configurable presence detect supports card and cable appli- cations ? gpe output pin for hot-plug event notification ? enables sci/smi generation for legacy operating system support ? hot-swap capable i/o ? power management ? supports d0, d3hot and d3 power management states ? active state power management (aspm) ? supports l0, l0s, l1, l2/l3 ready and l3 link states ? configurable l0s and l1 entry timers allow performance/ power-savings tuning 89HPES32T8G2 data sheet 32-lane 8-port pcie? gen2 i/o expansion switch
2 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet ? supports pci express power budgeting capability ? serdes power savings ? supports low swing / half-swing serdes operation ? serdes optionally turned-off in d3hot ? serdes associated with unused ports are turned-off ? serdes associated with unused lanes are placed in a low power state ? 9 general purpose i/o ? reliability, availability and serviceability (ras) ? ecrc support ? aer on all ports ? secded ecc protection on all internal rams ? end-to-end data path parity protection ? checksum serial eeprom content protected ? autonomous link reliability (preserves system operation in the presence of faulty links) ? ability to generate an interrupt (intx or msi) on link up/down transitions ? test and debug ? on-chip link activity and status outputs available for port 0 (upstream port) ? per port link activity and status outputs available using external i 2 c i/o expander for all other ports ? serdes test modes ? supports ieee 1149.6 ac jtag and ieee 1149.1 jtag ? power supplies ? requires only two power supply voltages (1.0 v and 2.5 v) note that a 3.3v is preferred for v dd i/o ? no power sequencing requirements ? packaged in a 23mm x 23mm 484- ball flip chip bga with 1mm ball spacing product description utilizing standard pci express interconnect, the pes32t8g2 provides the most efficient fan-out solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. it provides 32 gbps (256 gbps) of aggregated, full-duplex switching capacity through 32 integrated serial lanes, using proven and robust idt technology. each lane provides 5 gt/s of band- width in both directions and is fully compliant with pci express base specification, revision 2.0. the pes32t8g2 is based on a flexible and efficient layered archi- tecture. the pci express layer consists of serdes, physical, data link and transaction layers in compliance with pci express base specifica- tion revision 2.0. the pes32t8g2 can operate either as a store and forward or cut-through switch. it supports eight traffic classes (tcs) and one virtual channel (vc) with sophisticated resource management to enable efficient switching and i/o connectivity for servers, storage, and embedded processors with limited connectivity.
3 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet block diagram i figure 1 internal block diagram smbus interface the pes32t8g2 contains two smbus interfaces. the slave interfac e provides full access to the configuration registers in the pes 32t8g2, allowing every configuration register in the device to be read or written by an external agent. the master interface allows the default configuration register values of the pes32t8g2 to be overridden following a rese t with values programmed in an external serial eeprom. the ma ster interface is also used by an external hot-plug i/o expander. each of the two smbus interfaces contain an smbus clock pin and an smbus data pin. in addition, the slave smbus has ssmbaddr1 a nd ssmbaddr2 pins. as shown in figure 2, the master and sl ave smbuses may only be used in a split configuration. figure 2 split smbus interface configuration the switch?s smbus master interface does not support smbus arbitrat ion. as a result, the switch?s smbus master must be the only master in the smbus lines that connect to the serial eeprom and i/o expander slav es. in the split configuration, the master and slave smbuses operate as two independent buses; thus, multi-master arbitration is not required. 8-port switch core / 32 gen2 pci express lanes frame buffer route table port arbitration scheduler serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer serdes phy logical layer serdes phy logical layer serdes phy logical layer multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer (port 0) (port 1) (port 7) processor switch ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom ... hot-plug i/o expander
4 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet hot-plug interface the pes32t8g2 supports pci express hot-plug on each downstream por t. to reduce the number of pins required on the device, the p es32t8g2 utilizes an external i/o expander, such as that used on pc mother boards, connected to the smbus master interface. following res et and configura- tion, whenever the state of a hot-plug output needs to be modifi ed, the pes32t8g2 generates an smbus transaction to the i/o exp ander with the new value of all of the outputs. whenever a hot-plug input changes, the i/o expander generates an interrupt which is received o n the ioexpintn input pin (alternate function of gpio) of the pes32t8g2. in response to an i/o expander interrupt, the pes32t8g2 generates an s mbus transaction to read the state of all of the hot-plug inputs from the i/o expander. general purpose input/output the pes32t8g2 provides 9 general purpose input/output (gpio) pi ns that may be used by the system designer as bit i/o ports. eac h gpio pin may be configured independently as an input or output through software control. some gpio pins are shared with other on-chip fu nctions. these alternate functions may be enabled via software, smbus sl ave interface, or serial configuration eeprom.
5 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pin description the following tables list the functions of the pins provided on the pes32t8g2. some of the functions listed may be multiplexed onto the same pin. the active polarity of a signal is defined using a suffix. si gnals ending with an ?n? are defined as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses, and select lines ) will be interpreted as being active, or asserted, when at a logic one (high) level. signal type name/description pe00rp[3:0] pe00rn[3:0] i pci express port 0 serial data receive. differential pci express receive pairs for port 0. pe00tp[3:0] pe00tn[3:0] o pci express port 0 serial data transmit. differential pci express trans- mit pairs for port 0. pe01rp[3:0] pe01rn[3:0] i pci express port 1 serial data receive. differential pci express receive pairs for port 1. when port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. pe01tp[3:0] pe01tn[3:0] o pci express port 1 serial data transmit. differential pci express trans- mit pairs for port 1. when port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. pe02rp[3:0] pe02rn[3:0] i pci express port 2 serial data receive. differential pci express receive pairs for port 2. pe02tp[3:0] pe02tn[3:0] o pci express port 2 serial data transmit. differential pci express trans- mit pairs for port 2. pe03rp[3:0] pe03rn[3:0] i pci express port 3 serial data receive. differential pci express receive pairs for port 3. when port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. pe03tp[3:0] pe03tn[3:0] o pci express port 3 serial data transmit. differential pci express trans- mit pairs for port 3. when port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. pe04rp[3:0] pe04rn[3:0] i pci express port 4 serial data receive. differential pci express receive pairs for port 4. pe04tp[3:0] pe04tn[3:0] o pci express port 4 serial data transmit. differential pci express trans- mit pairs for port 4. pe05rp[3:0] pe05rn[3:0] i pci express port 5 serial data receive. differential pci express receive pairs for port 5. when port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. pe05tp[3:0] pe05tn[3:0] o pci express port 5 serial data transmit. differential pci express trans- mit pairs for port 5. when port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. pe06rp[3:0] pe06rn[3:0] i pci express port 6 serial data receive. differential pci express receive pairs for port 6. pe06tp[3:0] pe06tn[3:0] o pci express port 6 serial data transmit. differential pci express trans- mit pairs for port 6. pe07rp[3:0] pe07rn[3:0] i pci express port 7 serial data receive. differential pci express receive pairs for port 7. when port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. pe07tp[3:0] pe07tn[3:0] o pci express port 7 serial data transmit. differential pci express trans- mit pairs for port 7. when port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. table 1 pci express interface pins
6 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet signal type name/description gclkn[1:0] gclkp[1:0] i global reference clock. differential reference clock input pair. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic. the frequency of the differential reference clock is determined by the gclkfsel signal. table 2 reference clock pins signal type name/description msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. msmbdat i/o master smbus data. this bidirectional signal is used for data on the mas- ter smbus. ssmbaddr[2,1] i slave smbus address. these pins determine the smbus address to which the slave smbus interface responds. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize trans- fers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. table 3 smbus interface pins signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function ? reserved 2nd alternate function pin name: p0linkupn 2nd alternate function pin type: output 2nd alternate function: port 0 link up status output. gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function pin name: gpen 1st alternate function pin type: output 1st alternate function: hot-plug general purpose even output. 2nd alternate function pin name: p0activen 2nd alternate function pin type: output 2nd alternate function: port 0 link active status output. table 4 general purpose i/o pins (part 1 of 2)
7 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn alternate function pin type: input alternate function: io expander interrupt. signal type name/description clkmode[1:0] clock mode. these signals determine the port clocking mode used by ports of the device. gclkfsel i global clock frequency select. these signals select the frequency of the gclkp and gclkn signals. 0x0 100 mhz 0x1 125 mhz p01mergen i port 0 and 1 merge. p01mergen is an active low signal. it is pulled low internally. when this pin is low, port 0 is merged with port 1 to form a single x8 port. the serdes lanes associated with port 1 become lanes 4 through 7 of port 0. when this pin is high, port 0 and port 1 are not merged, and each operates as a single x4 port. p23mergen i port 2 and 3 merge. p23mergen is an active low signal. it is pulled low internally. when this pin is low, port 2 is merged with port 3 to form a single x8 port. the serdes lanes associated with port 3 become lanes 4 through 7 of port 2. when this pin is high, port 2 and port 3 are not merged, and each operates as a single x4 port. p45mergen i port 4 and 5 merge. p45mergen is an active low signal. it is pulled low internally. when this pin is low, port 4 is merged with port 5 to form a single x8 port. the serdes lanes associated with port 5 become lanes 4 through 7 of port 4. when this pin is high, port 4 and port 5 are not merged, and each operates as a single x4 port. p67mergen i port 6 and 7 merge. p67mergen is an active low signal. it is pulled low internally. when this pin is low, port 6 is merged with port 7 to form a single x8 port. the serdes lanes associated with port 7 become lanes 4 through 7 of port 6. when this pin is high, port 6 and port 7 are not merged, and each operates as a single x4 port. table 5 system pins (part 1 of 2) signal type name/description table 4 general purpose i/o pins (part 2 of 2)
8 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet perstn i global reset. assertion of this signal resets all logic inside pes32t8g2. rsthalt i reset halt. when this signal is asserted during a pci express fundamental reset, pes32t8g2 executes the reset procedure and remains in a reset state with the master and slave smbuses active. this allows software to read and write registers internal to the device before normal device opera- tion begins. the device exits the reset state when the rsthalt bit is cleared in the swctl register by an smbus master. swmode[3:0] i switch mode. these configuration pins determine the pes32t8g2 switch operating mode. note: these pins should be static and not change follow- ing the negation of perstn. 0x0 - normal switch mode 0x1 - normal switch mode with serial eeprom initialization 0x2 through 0x7 - reserved 0x8 - single partition with port 0 selected as the upstream port (port 2 dis- abled) 0x9 - single partition with port 2 selected as the upstream port (port 0 dis- abled) 0xa - single partition with serial eeprom initialization and port 0 selected as the upstream port (port 2 disabled) 0xb - single partition with serial eeprom initialization and port 2 selected as the upstream port (port 0 disabled) 0xe - reserved 0xf - reserved signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 6 test pins signal type name/description table 5 system pins (part 2 of 2)
9 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet signal type name/description refres00 i/o port 0 external reference resistor. provides a reference for the port 0 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres01 i/o port 1 external reference resistor. provides a reference for the port 1 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres02 i/o port 2 external reference resistor. provides a reference for the port 2 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres03 i/o port 3 external reference resistor. provides a reference for the port 3 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres04 i/o port 4 external reference resistor. provides a reference for the port 4 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres05 i/o port 5 external reference resistor. provides a reference for the port 5 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres06 i/o port 6 external reference resistor. provides a reference for the port 6 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refres07 i/o port 7 external reference resistor. provides a reference for the port 7 serdes bias currents and pll calibration circuitry. a 3 kohm +/- 1% resis- tor should be connected from this pin to ground. refrespll i/o pll external reference resistor. provides a reference for the pll bias currents and pll calibration circuitry. a 3k ohm +/- 1% resistor should be connected from this pin to ground. v dd core i core v dd. power supply for core logic (1.0v). v dd i/o i i/o v dd. lvttl i/o buffer power supply (2.5v or preferred 3.3v). v dd pea i pci express analog power. serdes analog power supply (1.0v). v dd peha i pci express analog high power. serdes analog power supply (2.5v). v dd peta i pci express transmitter analog voltage. serdes transmitter analog power supply (1.0v). v ss i ground. table 7 power, ground, and serdes resistor pins
10 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pin characteristics note: some input pads of the switch do not contain internal pull-ups or pull-downs. unused smbus and system inputs should be tied off to appropriate levels. this is especially critical for unused contro l signal inputs which, if left floating, could adversely affec t operation. also, floating pins can cause a slight increase in power consumption. unused serdes (rx and tx) pi ns should be left floating. finally, no conn ection pins should not be connected. function pin name type buffer i/o type internal resistor 1 notes pci express interface pe00rn[3:0] i pcie differential 2 serial link pe00rp[3:0] i pe00tn[3:0] o pe00tp[3:0] o pe01rn[3:0] i pe01rp[3:0] i pe01tn[3:0] o pe01tp[3:0] o pe02rn[3:0] i pe02rp[3:0] i pe02tn[3:0] o pe02tp[3:0] o pe03rn[3:0] i pe03rp[3:0] i pe03tn[3:0] o pe03tp[3:0] o pe04rn[3:0] i pe04rp[3:0] i pe04tn[3:0] o pe04tp[3:0] o pe05rn[3:0] i pe05rp[3:0] i pe05tn[3:0] o pe05tp[3:0] o pe06rn[3:0] i pe06rp[3:0] i pe06tn[3:0] o pe06tp[3:0] o pe07rn[3:0] i pe07rp[3:0] i pe07tn[3:0] o pe07tp[3:0] o gclkn[1:0] i hcsl diff. clock input refer to table 9 gclkp[1:0] i table 8 pin characteristics (part 1 of 2)
11 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet smbus msmbclk i/o lvttl sti 3 pull-up on board msmbdat i/o sti pull-up on board ssmbaddr[2,1] i input pull-up ssmbclk i/o sti pull-up on board ssmbdat i/o sti pull-up on board general purpose i/o gpio[8:0] i/o lvttl sti, high drive pull-up system pins clkmode[1:0] i lvttl input pull-up gclkfsel i pull-down p01mergen i pull-down p23mergen i pull-down p45mergen i pull-down p67mergen i pull-down perstn i sti rsthalt i input pull-down swmode[3:0] i pull-down ejtag / jtag jtag_tck i lvttl sti pull-up jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up serdes reference resistors refres00 i/o analog refres01 i/o refres02 i/o refres03 i/o refres04 i/o refres05 i/o refres06 i/o refres07 i/o refrespll i/o 1. internal resistor values under typical operating conditions are 92k for pull-up and 91k for pull-down. 2. all receiver pins set the dc common mode voltage to ground. all transmitters must be ac coupled to the media. 3. schmitt trigger input (sti). function pin name type buffer i/o type internal resistor 1 notes table 8 pin characteristics (part 2 of 2)
12 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet logic diagram ? pes32t8g2 figure 3 pes32t8g2 logic diagram pe00tp[3:0] global reference clocks gclkn[1:0] gclkp[1:0] jtag_tck gpio[8:0] 9 general purpose i/o v dd core v dd i/o v dd pea power/ground msmbclk msmbdat ssmbclk ssmbdat master smbus interface slave smbus interface gclkfsel rsthalt system pins jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag pins v ss swmode[3:0] 4 clkmode[1:0] perstn pe00rp[3:0] pe00rn[3:0] pci express switch serdes input pe00tn[3:0] pci express switch serdes output port 0 port 0 pe07rp[3:0] pe07rn[3:0] pci express switch serdes input pe07tp[3:0] pe07tn[3:0] pci express switch serdes output port 7 port 7 pes32t8g2 refres[7:0] serdes reference resistors v dd peha v dd peta ...... 2 p01mergen p23mergen pe01tp[3:0] pe01tn[3:0] pci express switch serdes output port 1 pe01rp[3:0] pe01rn[3:0] pci express switch serdes input port 1 ...... pe02rp[3:0] pe02rn[3:0] pci express switch serdes input port 2 pe02tp[3:0] pe02tn[3:0] pci express switch serdes output port 2 ssmbaddr[2,1] refrespll p45mergen p67mergen
13 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 13 and 14. ac timing characteristics parameter description condition min typical max unit refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency will be either 100 or 125 mhz depending on signal gclkfsel . mhz t c-rise rising edge rate differential 0.6 4 v/ns t c-fall falling edge rate differential 0.6 4 v/ns v ih differential input high voltage differential +150 mv v il differential input low voltage differential -150 mv v cross absolute single-ended crossing point voltage single-ended +250 +550 mv v cross-delta variation of v cross over all rising clock edges single-ended +140 mv v rb ring back voltage margin differential -100 +100 mv t stable time before v rb is allowed differential 500 ps t period-avg average clock period accuracy -300 2800 ppm t period-abs absolute period, including spread-spec- trum and jitter 9.847 10.203 ns t cc-jitter cycle to cycle jitter 150 ps v max absolute maximum input voltage +1.15 v v min absolute minimum input voltage -0.3 v duty cycle duty cycle 40 60 % rise/fall matching single ended rising refclk edge rate ver- sus falling refclk edge rate 20 % z c-dc clock source output dc impedance 40 60 table 9 input clock requirements parameter description gen 1 gen 2 units min 1 typ 1 max 1 min 1 typ 1 max 1 pcie transmit ui unit interval 399.88 400 400.12 199.94 200 200.06 ps t tx-eye minimum tx eye width 0.75 0.75 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.125 ui t tx-rise , t tx-fall tx rise/fall time: 20% - 80% 0.125 0.15 ui t tx- idle-min minimum time in idle 20 20 ui table 10 pcie ac timing characteristics (part 1 of 2)
14 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet t tx-idle-set-to-idle maximum time to transition to a valid idle after sending an idle ordered set 88 ns t tx-idle-to-diff- data maximum time to transition from valid idle to diff data 8 8 ns t tx-skew transmitter data skew between any 2 lanes 1.3 1.3 ns t min-pulsed minimum instantaneous lone pulse width na 0.9 ui t tx-hf-dj-dd transmitter deterministic jitter > 1.5mhz bandwidth na 0.15 ui t rf-mismatch rise/fall time differential mismatch na 0.1 ui pcie receive ui unit interval 399.88 400 400.12 199.94 200.06 ps t rx-eye (with jitter) minimum receiver eye width (jitter tolerance) 0.4 0.4 ui t rx-eye-medium to max jitter max time between jitter median & max deviation 0.3 ui t rx-skew lane to lane input skew 20 8 ns t rx-hf-rms 1.5 ? 100 mhz rms jitter (common clock) na 3.4 ps t rx-hf-dj-dd maximum tolerable dj by the receiver (common clock) na 88 ps t rx-lf-rms 10 khz to 1.5 mhz rms jitter (common clock) na 4.2 ps t rx-min-pulse minimum receiver instantaneous eye width na 0.6 ui 1. minimum, typical, and maximum values meet the requirements under pci specification 2.0 signal symbol reference edge min max unit timing diagram reference gpio gpio[8:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns table 11 gpio ac timing characteristics parameter description gen 1 gen 2 units min 1 typ 1 max 1 min 1 typ 1 max 1 table 10 pcie ac timing characteristics (part 2 of 2)
15 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet figure 4 jtag ac timing waveform signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 50.0 ? ns see figure 4. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to either the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 20 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ?20ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 12 jtag ac timing characteristics tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
16 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet recommended operating supply voltages power-up/power-down sequence during power supply ramp-up, v dd core must remain at least 1.0v below v dd i/o at all times. there are no other power-up sequence require- ments for the various operating supply voltages. the power-down sequence can occur in any order. recommended operating temperature symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes 2.25 2.5 2.75 v 3.125 3.3 3.465 v v dd pea 1 1. v dd pea and v dd peta should have no more than 25mv peak-peak ac power supply noise superimposed on the 1.0v nominal dc value. pci express analog power 0.95 1.0 1.1 v v dd peha 2 2. v dd peha should have no more than 50mv peak-peak ac power supply noise superimposed on the 2.5v nominal dc value. pci express analog high power 2.25 2.5 2.75 v v dd peta 1 pci express transmitter analog voltage 0.95 1.0 1.1 v v ss common ground 0 0 0 v table 13 pes32t8g2 operating voltages grade temperature commercial 0 c to +70 c ambient industrial -40 c to +85 c ambient table 14 pes32t8g2 operating temperatures
17 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet power consumption typical power is measured under the following conditions: 25c ambient, 35% total link usage on all ports, typical voltages def ined in table 13 (and also listed below). maximum power is measured under the following conditions: 70c ambient, 85% total link usage on all ports, maximum voltages def ined in table 13 (and also listed below). note 1 : i/o supply of 3.3v is preferred. note 2 : the above power consumption assumes that all ports are f unctioning at gen2 (5.0 gt/s) speeds. power consumption can be reduced by turning off unused ports through software or through boot eeprom. power savings will occur in v dd pea, v dd peha, and v dd peta. power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a t urned- off port is close to zero. for example, if 2 ports out of 8 are turned off, then the power savings for each of the above three power rails can be calculated quite simply as 2/8 multiplied by t he power consumption indicated in the above table. note 3 : using a port in gen1 mode (2.5gt/s) results in appr oximately 18% power savings for each power rail: v dd pea, v dd peha, and v dd peta. number of active lanes per port core supply pcie analog supply pcie analog high supply pcie transmitter supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 2.5v max 2.75v typ 1.0v max 1.1v typ 2.5v max 2.75v typ power max power 8/8/8/8 (full swing) ma 2850 5000 1514 1826 507 514 561 603 24 29 watts 2.85 5.50 1.51 2.01 1.27 1.41 0.56 0.66 0.06 0.08 6.25 9.67 8/8/8/8 (half swing) ma 2850 5000 1302 1571 507 514 292 313 24 29 watts 2.85 5.50 1.30 1.73 1.27 1.41 0.29 0.34 0.06 0.08 5.77 9.07 table 15 pes32t8g2 power consumption ? 2.5v i/o number of active lanes per port core supply pcie analog supply pcie analog high supply pcie transmitter supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 2.5v max 2.75v typ 1.0v max 1.1v typ 3.3v max 3.465v typ power max power 8/8/8/8 (full swing) ma 2850 5000 1514 1826 507 514 561 603 30 35 watts 2.85 5.50 1.51 2.01 1.27 1.41 0.56 0.66 0.10 0.12 6.29 9.71 8/8/8/8 (half swing) ma 2850 5000 1302 1571 507 514 292 313 30 35 watts 2.85 5.50 1.30 1.73 1.27 1.41 0.29 0.34 0.10 0.12 5.81 9.11 table 16 pes32t8g2 power consumption ? 3.3v i/o
18 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet thermal considerations this section describes thermal cons iderations for the pes32t8g2 (23mm 2 fcbga484 package). the data in table 17 below contains information that is relevant to the thermal performance of the pes32t8g2 switch. note: it is important for the reliability of this device in any us er environment that the junction temperature not exceed the t j(max) value specified in table 17. consequently, the effectiv e junction to ambient thermal resistance ( ja ) for the worst case scenario must be maintained below the value determined by the formula: ja = (t j(max) - t a(max) )/p given that the values of t j(max) , t a(max) , and p are known, the value of desired ja becomes a known entity to the system designer. how to achieve the desired ja is left up to the board or system designer, but in general, it can be achieved by adding the effects of jc (value provided in table 17), thermal resistance of the chosen adhesive ( cs ), that of the heat sink ( sa ), amount of airflow, and properties of the circuit board (number of layers and size of the board). it is strongly recommended that users perform their own thermal analysi s for their own board and system design scenarios. symbol parameter value units conditions t j(max) junction temperature 125 o c maximum t a(max) ambient temperature 70 o c maximum for commercial-rated products 85 o c maximum for industrial-rated products ja(effective) effective thermal resistance, junction-to-ambient 15.2 o c/w zero air flow 8.5 o c/w 1 m/s air flow 7.1 o c/w 2 m/s air flow jb thermal resistance, junction-to-board 3.1 o c/w jc thermal resistance, junction-to-case 0.15 o c/w p power dissipation of the device 9.71 watts maximum table 17 thermal specifications for pes32t8g2, 23x23 mm fcbga484 package
19 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet dc electrical characteristics values based on systems running at recommended supply voltages, as shown in table 13. note: see table 8, pin characteristics, for a complete i/o listing. i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 800 1200 mv v tx-diffp-p-low low-drive differential peak to peak output voltage 400 1200 400 1200 mv v tx-de-ratio- 3.5db de-emphasized differential output voltage -3 -4 -3.0 -3.5 -4.0 db v tx-de-ratio- 6.0db de-emphasized differential output voltage na -5.5 -6.0 -6.5 db v tx-dc-cm dc common mode voltage 0 3.6 0 3.6 v v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-dc-active- idle-delta abs delta of dc common mode voltage between l0 and idle 100 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 25 mv v tx-idle-diffp electrical idle diff peak output 20 20 mv rl tx-diff transmitter differential return loss 10 10 db 0.05 - 1.25ghz 8 db 1.25 - 2.5ghz rl tx-cm transmitter common mode return loss 66db z tx-diff-dc dc differential tx impedance 80 100 120 120 vtx-cm-acpp peak-peak ac common na 100 mv v tx-dc-cm transmit driver dc common mode voltage 0 3.6 0 3.6 v v tx-rcv-detect the amount of voltage change allowed during receiver detec- tion 600 600 mv i tx-short transmitter short circuit current limit 090 90ma table 18 dc electrical characteristics (part 1 of 2)
20 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet serial link (cont.) pcie receive v rx-diffp-p differential input voltage (peak-to- peak) 175 1200 120 1200 mv rl rx-diff receiver differential return loss 10 10 db 0.05 - 1.25ghz 8 1.25 - 2.5ghz rl rx-cm receiver common mode return loss 66db z rx-diff-dc differential input impedance (dc) 80 100 120 refer to return loss spec z rx--dc dc common mode impedance 40 50 60 40 60 z rx-comm-dc powered down input common mode impedance (dc) 200k 350k 50k z rx-high-imp-dc- pos dc input cm input impedance for v>0 during reset or power down 50k 50k z rx-high-imp-dc- neg dc input cm input impedance for v<0 during reset or power down 1.0k 1.0k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 65 175 mv v rx-cm-acp receiver ac common-mode peak voltage 150 150 mv v rx-cm-acp pcie refclk c in input capacitance 1.5 ? 1.5 ? pf other i/os low drive output i ol ?2.5? ?2.5 ? mav ol = 0.4v i oh ?-5.5? ?-5.5 ? mav oh = 1.5v high drive output i ol ? 12.0 ? ? 12.0 ? ma v ol = 0.4v i oh ? -20.0 ? ? -20.0 ? ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 2.0 ? v dd i/o + 0.5 v? input v il -0.3 ? 0.8 -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 2.0 ? v dd i/o + 0.5 v? capacitance c in ? ? 8.5 ? ? 8.5 pf ? leakage inputs ? ? + 10 ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 ? ? + 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 ? ? + 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 2.0. i/o type parameter description gen1 gen2 unit condi- tions min 1 typ 1 max 1 min 1 typ 1 max 1 table 18 dc electrical characteristics (part 2 of 2)
21 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet absolute maximum voltage rating warning: for proper and reliable operation in adherence with this data s heet, the device should not exceed the recommended operating vol tages in table 13. the absolute maximum operating voltages in table 19 are offered to provide guidelines for voltage excursions outsi de the recommended voltage ranges. device functionality is not guaranteed at these c onditions and sustained operation at these values or any expos ure to voltages outside the maximum range may adversely affect device functionality and reliability. smbus characterization core supply pcie analog supply pcie analog high supply pcie transmitter supply i/o supply 1.5v 1.5v 4.6v 1.5v 4.6v table 19 pes32t8g2 absolute maximum voltage rating symbol parameter smbus 2.0 char. data 1 1. data at room and hot temperature. unit 3v 3.3v 3.6v dc parameter for sda pin v il input low 1.16 1.26 1.35 v v ih input high 1.56 1.67 1.78 v v ol@350ua output low 15 15 15 mv i ol@0.4v 23 24 25 ma i pullup current source ? ? ? a i il_leak input low leakage 0 0 0 a i ih_leak input high leakage 0 0 0 a dc parameter for scl pin v il (v) input low 1.11 1.2 1.31 v v ih (v) input high 1.54 1.65 1.76 v i il_leak input low leakage 0 0 0 a i ih_leak input high leakage 0 0 0 a table 20 smbus dc characterization data
22 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet symbol parameter smbus @3.3v 10% 1 1. data at room and hot temperature. unit min max f scl clock frequency 5 600 khz t buf bus free time between stop and start 3.5 ? s t hd:sta start condition hold time 1 ? s t su:sta start condition setup time 1 ? s t su:sto stop condition setup time 1 ? s t hd:dat data hold time 1 ? ns t su:dat data setup time 1 ? ns t timeout detect clock low time out ? 74.7 ms t low clock low period 3.7 ? s t high clock high period 3.7 ? s t f clock/data fall time ? 72.2 ns t r clock/data rise time ? 68.3 ns t por@10khz time which a device must be operational after power-on reset 20 ? ms table 21 smbus ac timing data
23 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet package pinout ? 484-bga signal pinout the following table lists the pin numbers and signal names for the pes32t8g2 device. pin function alt pin function alt pin function alt pin function alt a1 v ss b13 v ss d3 v ss e15 v dd pea a2 v dd i/o b14 v ss d4 v ss e16 v ss a3 pe03tp3 b15 v ss d5 pe03rp3 e17 pe02rp1 a4 pe03tp2 b16 pe02tn1 d6 pe03rn2 e18 v dd peha a5 v ss b17 pe02tn0 d7 v ss e19 v ss a6 pe03tp1 b18 v dd i/o d8 pe03rp1 e20 v ss a7 pe03tp0 b19 msmbclk d9 v ss e21 pe00tn0 a8 v ss b20 jtag_tms d10 pe03rp0 e22 pe00tp0 a9 gclkp0 b21 ssmbclk d11 refrespll f1 v ss a10 v ss b22 jtag_tck d12 v ss f2 v ss a11 pe02tp3 c1 v ss d13 pe02rp3 f3 pe05rn3 a12 pe02tp2 c2 v dd i/o d14 v ss f4 pe05rp3 a13 v ss c3 v ss d15 pe02rp2 f5 v dd peha a14 v ss c4 v ss d16 v ss f6 v dd peha a15 v ss c5 pe03rn3 d17 pe02rn1 f7 v dd peha a16 pe02tp1 c6 v ss d18 pe02rp0 f8 v dd pea a17 pe02tp0 c7 v ss d19 v ss f9 v dd peta a18 v dd i/o c8 pe03rn1 d20 jtag_tdi f10 v dd pea a19 msmbdat c9 v ss d21 v dd i/o f11 v dd pea a20 jtag_tdo c10 pe03rn0 d22 v dd i/o f12 v dd peta a21 clkmode1 c11 v ss e1 v ss f13 v dd peta a22 ssmbaddr2 c12 v ss e2 v ss f14 v dd pea b1 v ss c13 pe02rn3 e3 v ss f15 v dd pea b2 v dd i/o c14 v ss e4 v ss f16 v dd pea b3 pe03tn3 c15 pe02rn2 e5 v dd peha f17 v dd peha b4 pe03tn2 c16 refres02 e6 pe03rp2 f18 v dd peha b5 v ss c17 v ss e7 v dd pea f19 v dd peha b6 pe03tn1 c18 pe02rn0 e8 v dd pea f20 v ss b7 pe03tn0 c19 perstn e9 v dd peta f21 pe00tn1 b8 v ss c20 jtag_trst_n e10 v dd pea f22 pe00tp1 b9 gclkn0 c21 ssmbdat e11 refres03 g1 pe05tp3 b10 v ss c22 ssmbaddr1 e12 v dd peta g2 pe05tn3 b11 pe02tn3 d1 v ss e13 nc g3 v ss b12 pe02tn2 d2 v ss e14 v ss g4 pe05rn2 table 22 pes32t8g2 signal pin-out (part 1 of 4)
24 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet g5 pe05rp2 h20 v ss k13 v ss m6 v dd pea g6 v dd pea h21 v ss k14 v dd core m7 v ss g7 v ss h22 v ss k15 v dd core m8 v dd core g8 v dd core j1 v ss k16 v ss m9 v dd core g9 v dd core j2 v ss k17 v dd peta m10 v ss g10 v ss j3 pe05rn1 k18 refres01 m11 v dd core g11 v dd core j4 pe05rp1 k19 pe00rp2 m12 v dd core g12 v dd core j5 v dd peta k20 pe00rn2 m13 v ss g13 v ss j6 v dd peta k21 v ss m14 v dd core g14 v dd core j7 v ss k22 v ss m15 v dd core g15 v dd core j8 v dd core l1 pe05tp0 m16 v ss g16 v ss j9 v dd core l2 pe05tn0 m17 v dd pea g17 v dd pea j10 v ss l3 v ss m18 v dd pea g18 v dd pea j11 v dd core l4 v ss m19 v ss g19 pe00rp0 j12 v dd core l5 v dd pea m20 v ss g20 pe00rn0 j13 v ss l6 v dd pea m21 pe00tn3 g21 v ss j14 v dd core l7 v ss m22 pe00tp3 g22 v ss j15 v dd core l8 v dd core n1 pe04tp3 h1 pe05tp2 j16 v ss l9 v dd core n2 pe04tn3 h2 pe05tn2 j17 v dd peta l10 v ss n3 refres04 h3 refres05 j18 v dd peta l11 v dd core n4 pe04rn2 h4 v ss j19 refres00 l12 v dd core n5 pe04rp2 h5 v dd pea j20 nc l13 v ss n6 v dd pea h6 v dd pea j21 v ss l14 v dd core n7 v ss h7 v ss j22 v ss l15 v dd core n8 v dd core h8 v dd core k1 pe05tp1 l16 v ss n9 v dd core h9 v dd core k2 pe05tn1 l17 v dd pea n10 v ss h10 v ss k3 v ss l18 pe00rp3 n11 v dd core h11 v dd core k4 pe05rn0 l19 pe00rn3 n12 v dd core h12 v dd core k5 pe05rp0 l20 v ss n13 v ss h13 v ss k6 v dd peta l21 pe00tn2 n14 v dd core h14 v dd core k7 v ss l22 pe00tp2 n15 v dd core h15 v dd core k8 v dd core m1 v ss n16 v ss h16 v ss k9 v dd core m2 v ss n17 v dd pea h17 v dd pea k10 v ss m3 pe04rn3 n18 v dd pea h18 pe00rp1 k11 v dd core m4 pe04rp3 n19 pe01rp0 h19 pe00rn1 k12 v dd core m5 v dd pea n20 pe01rn0 pin function alt pin function alt pin function alt pin function alt table 22 pes32t8g2 signal pin-out (part 2 of 4)
25 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet n21 v ss r14 v dd core u7 v dd pea v22 pe01tp3 n22 v ss r15 v dd core u8 v dd pea w1 v ss p1 pe04tp2 r16 v ss u9 v dd pea w2 p23mergen p2 pe04tn2 r17 v dd peta u10 v dd peta w3 p45mergen p3 v ss r18 v dd peta u11 v dd peta w4 v dd i/o p4 v ss r19 v ss u12 v dd pea w5 pe06rp0 p5 v dd peta r20 v ss u13 v dd pea w6 pe06rn1 p6 v dd peta r21 pe01tn1 u14 v dd pea w7 refres06 p7 v ss r22 pe01tp1 u15 v dd peta w8 pe06rp2 p8 v dd core t1 pe04tp1 u16 v dd pea w9 v ss p9 v dd core t2 pe04tn1 u17 v dd peha w10 v ss p10 v ss t3 v ss u18 pe01rp3 w11 pe06rp3 p11 v dd core t4 v ss u19 pe01rn3 w12 v ss p12 v dd core t5 v dd peha u20 v ss w13 pe07rp0 p13 v ss t6 v dd peha u21 pe01tn2 w14 pe07rn1 p14 v dd core t7 v ss u22 pe01tp2 w15 v ss p15 v dd core t8 v dd core v1 v dd i/o w16 pe07rp2 p16 v ss t9 v dd core v2 v dd i/o w17 v ss p17 v dd pea t10 v ss v3 pe04rn0 w18 v dd peha p18 pe01rp1 t11 v dd core v4 pe04rp0 w19 pe07rp3 p19 pe01rn1 t12 v dd core v5 v ss w20 v dd i/o p20 v ss t13 v ss v6 pe06rp1 w21 v dd i/o p21 pe01tn0 t14 v dd core v7 v ss w22 v dd i/o p22 pe01tp0 t15 v dd core v8 v dd pea y1 p01mergen r1 v ss t16 v ss v9 v dd pea y2 p67mergen r2 v ss t17 v dd peta v10 v ss y3 v ss r3 pe04rn1 t18 v dd peta v11 v dd peta y4 v ss r4 pe04rp1 t19 pe01rp2 v12 v ss y5 pe06rn0 r5 v dd peta t20 pe01rn2 v13 v dd pea y6 v ss r6 v dd peta t21 v ss v14 pe07rp1 y7 v ss r7 v ss t22 v ss v15 v dd peta y8 pe06rn2 r8 v dd core u1 pe04tp0 v16 v dd pea y9 v ss r9 v dd core u2 pe04tn0 v17 v dd peha y10 v ss r10 v ss u3 v ss v18 v dd peha y11 pe06rn3 r11 v dd core u4 v ss v19 v ss y12 v ss r12 v dd core u5 v dd peha v20 v ss y13 pe07rn0 r13 v ss u6 v dd peha v21 pe01tn3 y14 v ss pin function alt pin function alt pin function alt pin function alt table 22 pes32t8g2 signal pin-out (part 3 of 4)
26 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet alternate signal functions no connection pins y15 refres07 aa6 pe06tn0 aa19 v ss ab10 pe06tp3 y16 pe07rn2 aa7 pe06tn1 aa20 gpio_03 ab11 v ss y17 v ss aa8 v ss aa21 gpio_04 1 ab12 gclkp1 y18 v ss aa9 pe06tn2 aa22 gpio_05 2 ab13 v ss y19 pe07rn3 aa10 pe06tn3 ab1 swmode1 ab14 pe07tp0 y20 gpio_06 aa11 v ss ab2 rsthalt ab15 pe07tp1 y21 gpio_07 aa12 gclkn1 ab3 swmode2 ab16 v ss y22 gpio_08 1 aa13 v ss ab4 swmode3 ab17 pe07tp2 aa1 clkmode0 aa14 pe07tn0 ab5 v dd i/o ab18 pe07tp3 aa2 gclkfsel aa15 pe07tn1 ab6 pe06tp0 ab19 v ss aa3 swmode0 aa16 v ss ab7 pe06tp1 ab20 gpio_00 aa4 v ss aa17 pe07tn2 ab8 v ss ab21 gpio_01 aa5 v dd i/o aa18 pe07tn3 ab9 pe06tp2 ab22 gpio_02 pin gpio 1st alternate 2nd alternate aa21 gpio_04 ? p0linkupn aa22 gpio_05 gpen p0activen y22 gpio_08 ioexpintn ? table 23 pes32t8g2 alternate signal functions nc e13 j20 table 24 pes32t8g2 no connection pin function alt pin function alt pin function alt pin function alt table 22 pes32t8g2 signal pin-out (part 4 of 4)
27 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet power pins v dd core v dd core v dd core v dd io v dd pea v dd pea v dd peha v dd peta g8 k11 n14 a2 e7 m5 e5 e9 g9 k12 n15 a18 e8 m6 e18 e12 g11 k14 p8 b2 e10 m17 f5 f9 g12 k15 p9 b18 e15 m18 f6 f12 g14 l8 p11 c2 f8 n6 f7 f13 g15 l9 p12 d21 f10 n17 f17 j5 h8 l11 p14 d22 f11 n18 f18 j6 h9 l12 p15 v1 f14 p17 f19 j17 h11 l14 r8 v2 f15 u7 t5 j18 h12 l15 r9 w4 f16 u8 t6 k6 h14 m8 r11 w20 g6 u9 u5 k17 h15 m9 r12 w21 g17 u12 u6 p5 j8 m11 r14 w22 g18 u13 u17 p6 j9 m12 r15 aa5 h5 u14 v17 r5 j11 m14 t8 ab5 h6 u16 v18 r6 j12 m15 t9 h17 v8 w18 r17 j14 n8 t11 l5 v9 r18 j15 n9 t12 l6 v13 t17 k8 n11 t14 l17 v16 t18 k9 n12 t15 u10 u11 u15 v11 v15 table 25 pes32t8g2 power pins
28 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet ground pins v ss v ss v ss v ss v ss v ss a1 d3 h4 l10 r2 w10 a5 d4 h7 l13 r7 w12 a8 d7 h10 l16 r10 w15 a10 d9 h13 l20 r13 w17 a13d12h16m1r16y3 a14d14h20m2r19y4 a15d16h21m7r20y6 b1 d19 h22 m10 t3 y7 b5 e1 j1 m13 t4 y9 b8 e2 j2 m16 t7 y10 b10 e3 j7 m19 t10 y12 b13 e4 j10 m20 t13 y14 b14 e14 j13 n7 t16 y17 b15 e16 j16 n10 t21 y18 c1 e19 j21 n13 t22 aa4 c3 e20 j22 n16 u3 aa8 c4 f1 k3 n21 u4 aa11 c6 f2 k7 n22 u20 aa13 c7 f20 k10 p3 v5 aa16 c9 g3 k13 p4 v7 aa19 c11 g7 k16 p7 v10 ab8 c12 g10 k21 p10 v12 ab11 c14 g13 k22 p13 v19 ab13 c17 g16 l3 p16 v20 ab16 d1 g21 l4 p20 w1 ab19 d2 g22 l7 r1 w9 ? table 26 pes32t8g2 ground pins
29 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet signals listed alphabetically signal name i/o type location signal category clkmode0 i aa1 system clkmode1 i a21 gclkfsel i aa2 gclkn0 i b9 pci express gclkn1 i aa12 gclkp0 i a9 gclkp1 i ab12 gpio_00 i/o ab20 general purpose input/output gpio_01 i/o ab21 gpio_02 i/o ab22 gpio_03 i/o aa20 gpio_04 i/o aa21 gpio_05 i/o aa22 gpio_06 i/o y20 gpio_07 i/o y21 gpio_08 i/o y22 jtag_tck i b22 jtag jtag_tdi i d20 jtag_tdo o a20 jtag_tms i b20 jtag_trst_n i c20 msmbclk i/o b19 smbus msmbdat i/o a19 no connection see table 24 for a listing of no connect pins. p01mergen i y1 system p23mergen i w2 p45mergen i w3 p67mergen i y2 table 27 pes32t8g2 alphabetical signal list (part 1 of 6)
30 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pe00rn0 i g20 pci express pe00rn1 i h19 pe00rn2 i k20 pe00rn3 i l19 pe00rp0 i g19 pe00rp1 i h18 pe00rp2 i k19 pe00rp3 i l18 pe00tn0 o e21 pe00tn1 o f21 pe00tn2 o l21 pe00tn3 o m21 pe00tp0 o e22 pe00tp1 o f22 pe00tp2 o l22 pe00tp3 o m22 pe01rn0 i n20 pe01rn1 i p19 pe01rn2 i t20 pe01rn3 i u19 pe01rp0 i n19 pe01rp1 i p18 pe01rp2 i t19 pe01rp3 i u18 pe01tn0 o p21 pe01tn1 o r21 pe01tn2 o u21 pe01tn3 o v21 pe01tp0 o p22 pe01tp1 o r22 pe01tp2 o u22 pe01tp3 o v22 pe02rn0 i c18 pe02rn1 i d17 pe02rn2 i c15 pe02rn3 i c13 signal name i/o type location signal category table 27 pes32t8g2 alphabetical signal list (part 2 of 6)
31 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pe02rp0 i d18 pci express (cont.) pe02rp1 i e17 pe02rp2 i d15 pe02rp3 i d13 pe02tn0 o b17 pe02tn1 o b16 pe02tn2 o b12 pe02tn3 o b11 pe02tp0 o a17 pe02tp1 o a16 pe02tp2 o a12 pe02tp3 o a11 pe03rn0 i c10 pe03rn1 i c8 pe03rn2 i d6 pe03rn3 i c5 pe03rp0 i d10 pe03rp1 i d8 pe03rp2 i e6 pe03rp3 i d5 pe03tn0 o b7 pe03tn1 o b6 pe03tn2 o b4 pe03tn3 o b3 pe03tp0 o a7 pe03tp1 o a6 pe03tp2 o a4 pe03tp3 o a3 pe04rn0 i v3 pe04rn1 i r3 pe04rn2 i n4 pe04rn3 i m3 pe04rp0 i v4 pe04rp1 i r4 pe04rp2 i n5 pe04rp3 i m4 signal name i/o type location signal category table 27 pes32t8g2 alphabetical signal list (part 3 of 6)
32 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pe04tn0 o u2 pci express (cont.) pe04tn1 o t2 pe04tn2 o p2 pe04tn3 o n2 pe04tp0 o u1 pe04tp1 o t1 pe04tp2 o p1 pe04tp3 o n1 pe05rn0 i k4 pe05rn1 i j3 pe05rn2 i g4 pe05rn3 i f3 pe05rp0 i k5 pe05rp1 i j4 pe05rp2 i g5 pe05rp3 i f4 pe05tn0 o l2 pe05tn1 o k2 pe05tn2 o h2 pe05tn3 o g2 pe05tp0 o l1 pe05tp1 o k1 pe05tp2 o h1 pe05tp3 o g1 pe06rn0 i y5 pe06rn1 i w6 pe06rn2 i y8 pe06rn3 i y11 pe06rp0 i w5 pe06rp1 i v6 pe06rp2 i w8 pe06rp3 i w11 pe06tn0 o aa6 pe06tn1 o aa7 pe06tn2 o aa9 pe06tn3 o aa10 signal name i/o type location signal category table 27 pes32t8g2 alphabetical signal list (part 4 of 6)
33 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pe06tp0 o ab6 pci express (cont.) pe06tp1 o ab7 pe06tp2 o ab9 pe06tp3 o ab10 pe07rn0 i y13 pe07rn1 i w14 pe07rn2 i y16 pe07rn3 i y19 pe07rp0 i w13 pe07rp1 i v14 pe07rp2 i w16 pe07rp3 i w19 pe07tn0 o aa14 pe07tn1 o aa15 pe07tn2 o aa17 pe07tn3 o aa18 pe07tp0 o ab14 pe07tp1 o ab15 pe07tp2 o ab17 pe07tp3 o ab18 perstn i c19 system refres00 i j19 serdes reference resistors refres01 i k18 refres02 i c16 refres03 i e11 refres04 i n3 refres05 i h3 refres06 i w7 refres07 i y15 refrespll i d11 rsthalt i ab2 system ssmbaddr1 i c22 smbus ssmbaddr2 i a22 ssmbclk i/o b21 ssmbdat i/o c21 signal name i/o type location signal category table 27 pes32t8g2 alphabetical signal list (part 5 of 6)
34 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet swmode0 i aa3 system swmode1 i ab1 swmode2 i ab3 swmode3 i ab4 v dd core, v dd- pea, v dd io, v dd pe , v tt pe see table 25 for a listing of power pins. v ss see table 26 for a listing of ground pins. signal name i/o type location signal category table 27 pes32t8g2 alphabetical signal list (part 6 of 6)
35 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pes32t8g2 pinout ? top view 12345678910111213141516 17 18 19 20 21 22 a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 1112 13141516 17 18 19 20 21 22 a b c d e f g h j k l m n p r t u v w y aa ab vss (ground) v dd core (power) v dd i/o (power) v dd peta (transmitter power) v dd pea (analog power) v dd peha (high analog power) signals no connect x x x x x x x x x x x x x x x x x x x x x x x x x x x
36 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pes32t8g2 package drawing ? 484-pin bl484/br484 www.idt.com t id
37 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet pes32t8g2 package drawing ? page two www.idt.com t id
38 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet revision history january 21, 2010 : publication of final data sheet. march 30, 2011 : in table 13, added v dd peta to footnote #1. november 28, 2011 : added new tables 20 and 21, smbus characterization and timing.
39 of 39 november 28, 2011 idt 89HPES32T8G2 data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89h32t8g2zbbl 484-ball fcbga package, commercial temperature 89h32t8g2zbblg 484-ball green fcbga package, commercial temperature 89h32t8g2zbbli 484-ball fcbga package, industrial temperature 89h32t8g2zbblgi 484-ball green fcbga package, industrial temperature 89h32t8g2zcbl 484-ball fcbga package, commercial temperature 89h32t8g2zcblg 484-ball green fcbga package, commercial temperature 89h32t8g2zcbli 484-ball fcbga package, industrial temperature 89h32t8g2zcblgi 484-ball green fcbga package, industrial temperature nn a nnann aa a operating voltage product package temp range h product family 89 serial switching product 32t8 32-lane, 8-port 1.0v +/- 0.1v core voltage detail legend a = alpha character n = numeric character aa device revision an generation series g2 pcie gen 2 484 484-ball fcbga bl 484 484-ball fcbga, green blg blank commercial temperature (0c to +70c ambient) i industrial temperature (-40 c to +85 c ambient) zb zb revision zc zc revision

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